The cin bit is considered to be valid only on the first clock cycle after a low reset. And in each clock cycle we get the corresponding bit on output s. The design keeps adding the input bits in a serial way, when the reset is not high. Note that, even though this code works as a N-bit adder, we don't have to mention the value of N directly. generate clock with 10 ns clock period. If ( reset = 1 ) begin //active high resetĬ = cin //on first iteration after reset, assign cin to c.įlag = 1 //then make flag 1, so that this if statement isnt executed any more.Ĭ = ( a & b ) | ( c & b ) | ( a & c ) //CARRY Output reg s, cout //note that s comes out at every clock cycle and cout is valid only for last clock cycle. Input a, b, cin, //note that cin is used for only first iteration. Note that we dont have to mention N here. Though I have used behavioral level approach to write my code, it should be straight forward to understand if you have the basics right. In this post, I have used a similar idea to implement the serial adder. The D flipflop is used to pass the output carry, back to the full adder with a clock cycle delay. The above block diagram shows how a serial adder can be implemented.
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